`timescale 1ns/1ps
module uart_tb (
    
);
    reg clk;
    reg rstn;
    wire uart_tx;


    uartTop u_uartTop(
        .clk  ( clk  ),
        .rstn ( rstn ),
        .uart_tx  ( uart_tx  )
    );

    initial begin
        clk = 0;
        rstn = 0;
        #201;
        rstn = 1;

        #50000000;
    end
    always #10 clk = ~clk;
endmodule //uart_tb